Semiconductor device and method of manufacturing a semiconductor device

ABSTRACT

A semiconductor device comprises: a semiconductor substrate; a gate insulating film formed on the top surface of the semiconductor substrate; a gate electrode formed on the gate insulating film; diffusion layers formed in the semiconductor substrate to be used a source layer and a drain layer; and a silicide layer formed to overlie the diffusion layers; wherein an oxygen concentration peak, where oxygen concentration is maximized, is at a level lower than said top surface in a cross-section taken along a plane perpendicular to said top surface.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application(s) No(s). 2002-23548, filed onJan. 31, 2002, the entire contents of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a semiconductor device and a method ofmanufacturing a semiconductor device.

2. Related Background Art

Integrated circuits having MOS transistors are becoming more and moreenhanced in terms of microminiaturization and operation speed. Toprevent short-channeling effects such as punch-through along with themicrominiaturization of MOS transistors, relatively shallow source anddrain diffusion layers are formed.

To ensure high-speed operations of MOS transistors, the SALCIDE(Self-Aligned Silicide) technique is frequently used, as it reduces thecontact resistance between the diffusion layers and a metal by forming asilicide layer on the diffusion layers in self-alignment. In theSALICIDE technique, silicide is formed by the interaction between thedeposited metal and silicon as the substrate material. Therefore, incase a metal is directly deposited on shallow source and drain diffusionlayers, silicide often appears after being downwardly thrust through thediffusion layers. As a result, leakage occurs between the source anddrain diffusion layers and the substrate.

As a countermeasure, the Elevated Source-Drain technique has beendeveloped. This is a technique that forms a silicide layer by depositinga metal on a silicon single-crystal layer selectively formed on thesource and drain regions. Since the silicon of the siliconsingle-crystal layer interacts with the metal and forms the silicide,the silicide does not excessively erode the source or drain diffusionlayers. Therefore, it was expected that the downward penetration of thesilicide through the source or drain diffusion layer was prevented.

In the Elevated Source-Drain technique, silicon is epitaxially grown onthe source and drain diffusion layers, which are limited regions of theentire surface of the semiconductor substrate. In order to obtain asufficiently thick silicon single-crystal layer by the epitaxial growthprocess, the vapor-phase epitaxy (VPE) technique needs annealing at ahigh temperature not lower than 800° C.

Such high-temperature annealing, however, causes thermal diffusion ofimpurities in the source and drain diffusion layers. In the epitaxialgrowth process, excessive diffusion of these diffusion layers may invitethe short-channeling effect in miniaturized MOS transistors. Therefore,high-temperature annealing of semiconductor substrates is not desirableafter sources and drains are formed.

Apart from this, there is the Solid Phase Epitaxy (SPE) technique thatfirst deposits amorphous silicon on a semiconductor substrate andthereafter anneals it at approximately 600° C. to change the silicon tosingle crystal. Even with the Solid Phase Epitaxy, a siliconsingle-crystal layer can be formed on source and drain diffusion layers.When annealing is carried out at a relatively low temperature around600° C., thermal diffusion of source and drain diffusion layers isimmaterial.

However, even in Solid Phase Epitaxy, if a silicon oxide exists on thesemiconductor substrate, amorphous silicon deposited on the siliconoxide sometimes fails to change to single crystal. In this case,amorphous silicon on the source and drain diffusion layers can change tosingle crystal only partly and insufficiently for use in the ElevatedSource-Drain technique. As a result, in a step of selectively etchingthe amorphous silicon deposited on the top surface of the semiconductorsubstrate, the silicon having failed to change to single crystal onsource and drain regions is undesirably etched simultaneously.Therefore, this technique could not make the best use of the ElevatedSource-Drain technique.

Especially when the semiconductor substrate is a p-type substratecontaining an impurity such as boron, because it is easily oxidized,amorphous silicon deposited on the top surface of the p-typesemiconductor substrate containing boron, or the like, is difficult tosingle-crystallize sufficiently.

These and other problems involved in the conventional techniques arediscussed below with reference to the drawings.

FIGS. 20 through 24 are cross-sectional views that show a semiconductorsubstrate in an enlarged form to demonstrate a conventional method ofmanufacturing a semiconductor device in the order of its procedures.

As shown in FIG. 20, an isolating region 30 is formed in thesemiconductor substrate 10. The substrate 10 has formed a gateinsulating film 40 on its top surface and a gate electrode 60 on thegate insulating film 40. A sidewall protective layer 85 is formed on thesidewall of the gate electrode. The semiconductor substrate 10 furtherincludes diffusion layers 70, 72 as source and drain layers.

The top surface of the semiconductor substrate 10 in the regions of thediffusion layers 70, 72 are exposed to epitaxially grow a siliconsingle-crystal layer thereon. However, the top surface of thesemiconductor substrate 10 is oxidized when contacting air, and asilicon oxide 90 is produced on the top surface of the semiconductorsubstrate.

As shown in FIG. 21, an amorphous silicon layer 100 is deposited on thetop surface of the semiconductor substrate and on the gate electrode 60.

As shown in FIG. 22, the amorphous silicon layer 100 is annealed.However, the silicon oxide 90 exists between the top surface of thesemiconductor substrate 10 and the amorphous silicon layer 100, andlocally prevents the amorphous silicon layer 90 from direct contact withthe top surface of the semiconductor substrate 10. Since the amorphoussilicon layer 100 can epitaxially grow only along the crystal on the topsurface of the semiconductor substrate 10, part of the amorphous siliconlayer 100 not contacting the top surface of the semiconductor substrate10 cannot grow epitaxially even when it is annealed. As a result, thesilicon single-crystal layer 120 transformed from the amorphous siliconlayer 100 by annealing does not become uniform in thickness and qualityon the top surface of the semiconductor substrate 10.

As shown in FIG. 23, as a result of etching by making use of thedifference in etching rate between the silicon single-crystal layer andthe amorphous or polycrystalline silicon, the amorphous silicon 100 andthe polycrystalline silicon transformed from the amorphous silicon 100are etched, and the silicon single-crystal layer 120 remains.

As shown in FIG. 24, a metal acts on the silicon deposited on thesemiconductor substrate 10, as a result, a silicide layer 130 is formed.In regions where the silicon single-crystal layer 120 is thin, thedeposited metal acts not only on the silicon of the siliconsingle-crystal layer 120 but also on the silicon of the diffusion layers70, 72. Therefore, the diffusion layers 70, 72 are excessivelyencroached by the silicide layer 130, which may grow even beyond thediffusion layers 70, 72. Thus, the advantage of the ElevatedSource-Drain technique is not harnessed sufficiently.

Here is needed a semiconductor device manufacturing method capable offorming a silicon single-crystal layer acceptable for use with theElevated Source-Drain technique on source and drain diffusion layers ata relatively low temperature.

Additionally needed is a semiconductor device having a silicide layerformed by the Elevated Source-Drain technique and uniform in thicknessand quality, keeping the contact resistance low between the source anddrain diffusion layers on one part and source and drain electrodes onthe other part, and available for more progressed microminiaturizationthan a conventional one.

BRIEF SUMMARY OF THE INVENTION

A semiconductor device according to an embodiment of the inventioncomprises: a semiconductor substrate; a gate insulating film formed onthe top surface of the semiconductor substrate; a gate electrode formedon the gate insulating film; diffusion layers formed in thesemiconductor substrate to be used a source layer and a drain layer; anda silicide layer formed to overlie the diffusion layers;

-   -   wherein an oxygen concentration peak, where oxygen concentration        is maximized, is at a level lower than said top surface in a        cross-section taken along a plane perpendicular to said top        surface.

A method of manufacturing a semiconductor device according to anembodiment of the invention comprises: forming a gate insulating film onthe top surface of a semiconductor substrate; forming a gate electrodeon the gate insulating film; forming diffusion layers in a self-alignedmanner in the semiconductor substrate on opposite sides of the gateelectrode; forming an amorphous layer on the top surface of thesemiconductor substrate above the diffusion layers; implanting ions ofan injection substance into the semiconductor substrate through aninterface thereof with the amorphous layer; annealing the semiconductorsubstrate at a relatively low temperature to partly change the amorphouslayer to a single-crystal layer; and sputtering a metal onto thesingle-crystal layer and thereby forming a silicide layer from thesingle crystal and the metal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an enlarged cross-sectional view of a semiconductor substrateunder a process of a semiconductor device manufacturing method accordingto the first embodiment of the invention;

FIG. 2 is an enlarged cross-sectional view of the semiconductorsubstrate under a process continuous from FIG. 1 in the semiconductordevice manufacturing method according to the first embodiment;

FIG. 3 is an enlarged cross-sectional view of the semiconductorsubstrate under a process continuous from FIG. 2 in the semiconductordevice manufacturing method according to the first embodiment;

FIG. 4 is an enlarged cross-sectional view of the semiconductorsubstrate under a process continuous from FIG. 3 in the semiconductordevice manufacturing method according to the first embodiment;

FIG. 5 is an enlarged cross-sectional view of the semiconductorsubstrate under a process continuous from FIG. 4 in the semiconductordevice manufacturing method according to the first embodiment;

FIG. 6 is an enlarged cross-sectional view of the semiconductorsubstrate under a process continuous from FIG. 5 in the semiconductordevice manufacturing method according to the first embodiment;

FIG. 7 is an enlarged cross-sectional view of the semiconductorsubstrate under a process continuous from FIG. 6 in the semiconductordevice manufacturing method according to the first embodiment;

FIG. 8 is an enlarged cross-sectional view of the semiconductorsubstrate under a process continuous from FIG. 7 in the semiconductordevice manufacturing method according to the first embodiment;

FIG. 9 is an enlarged cross-sectional view of the semiconductorsubstrate under a process continuous from FIG. 8 in the semiconductordevice manufacturing method according to the first embodiment;

FIG. 10 is an enlarged cross-sectional view of the semiconductorsubstrate under a process continuous from FIG. 9 in the semiconductordevice manufacturing method according to the first embodiment;

FIG. 11A is an enlarged cross-sectional view of a semiconductor device200 manufactured by a semiconductor device manufacturing methodaccording to the first embodiment;

FIG. 11B is a graph showing changes of oxygen and germaniumconcentrations with depth from the top surface 12 of the semiconductordevice 200;

FIG. 12 is an enlarged cross-sectional view of a semiconductor substrateunder a process of a semiconductor device manufacturing method accordingto the second embodiment of the invention;

FIG. 13 is an enlarged cross-sectional view of the semiconductorsubstrate under a process continuous from FIG. 12 in the semiconductordevice manufacturing method according to the second embodiment;

FIG. 14 is an enlarged cross-sectional view of the semiconductorsubstrate under a process continuous from FIG. 13 in the semiconductordevice manufacturing method according to the second embodiment;

FIG. 15 is an enlarged cross-sectional view of the semiconductorsubstrate under a process continuous from FIG. 14 in the semiconductordevice manufacturing method according to the second embodiment;

FIG. 16 is an enlarged cross-sectional view of the semiconductorsubstrate under a process continuous from FIG. 15 in the semiconductordevice manufacturing method according to the second embodiment;

FIG. 17 is an enlarged cross-sectional view of the semiconductorsubstrate under a process continuous from FIG. 16 in the semiconductordevice manufacturing method according to the second embodiment;

FIG. 18 is an enlarged cross-sectional view of the semiconductorsubstrate under a process continuous from FIG. 17 in the semiconductordevice manufacturing method according to the second embodiment;

FIG. 19 is an enlarged cross-sectional view of the semiconductorsubstrate under a process continuous from FIG. 18 in the semiconductordevice manufacturing method according to the second embodiment;

FIG. 20 is an enlarged cross-sectional view of a semiconductor substrateunder a process of a conventional semiconductor device manufacturingprocess;

FIG. 21 is an enlarged cross-sectional view of a semiconductor substrateunder a process of a conventional semiconductor device manufacturingprocess;

FIG. 22 is an enlarged cross-sectional view of a semiconductor substrateunder a process of the conventional semiconductor device manufacturingprocess;

FIG. 23 is an enlarged cross-sectional view of a semiconductor substrateunder a process of the conventional semiconductor device manufacturingprocess; and

FIG. 24 is an enlarged cross-sectional view of a semiconductor substrateunder a process of the conventional semiconductor device manufacturingprocess.

DETAILED DESCRIPTION OF THE INVENTION

Some embodiments of the invention will now be explained below withreference to the drawings. However, these embodiments should not beconstrued to limit the invention, and respective components shown in thedrawings may not accord with their scale.

FIGS. 1 through 10 are enlarged cross-sectional views of a semiconductorsubstrate for sequentially showing a semiconductor device manufacturingmethod according to the first embodiment of the invention. In thisembodiment, a p-type MOS transistor is manufactured.

As shown in FIG. 1, an n-type well region 20 is formed by introducingarsenic, phosphorus or other impurity into a semiconductor substrate 10and annealing it. In this embodiment, the depth of the n-type wellregion 20 from the top surface 12 of the semiconductor substrate 10 isabout 1 μm.

After that, an isolation 30 is formed by burying an oxide in apredetermined region. In this embodiment, the isolation 30 is made bythe STI (shallow trench isolation) technique. The depth of the isolation30 from the top surface 12 of the semiconductor substrate 10 is about400 nm.

As shown in FIG. 2, a substrate protective oxide film 48 is next formedon the top surface 12 of the semiconductor substrate 10. The substrateprotective oxide film 48 is used to protect the substrate 10 against theimpulse of subsequent channel-ion injection 58. In this embodiment, thethickness of the substrate protective oxide film 48 is about 10 nm.Thereafter, channel-ion injection 58 is carried out to adjust thethreshold voltage of the MOS transistor.

As shown in FIG. 3, after the substrate protective oxide film 48 is nextremoved, a gate insulating film 40 is formed on the top surface 12 ofthe semiconductor substrate 10. The thickness of the gate insulatingfilm 40 is approximately several nanometers. The gate insulating film 40may be a silicon oxide film, but also usable is an oxynitride film madeby introducing several % of nitrogen into a silicon oxide film, an highdielectric constant such as TaO₂, ZrO_(x), HfO_(x) (where x is apositive integer), or any of their silicate film.

After that, polycrystalline silicon is deposited on the gate insulatingfilm 40 by CVD (chemical vapor deposition), for example. Thereafter, agate electrode 60 is formed by patterning the deposited polycrystallinesilicon by photolithography. In the instant embodiment, the thickness ofthe gate electrode 60 is around 150 nm.

As shown in FIG. 4, ion injection 75 is next carried out to form adiffusion layer 70. The diffusion layer 70 is formed in a self-alignedmanner in opposite sides of the gate electrode 60 by introducing ions tothe top surface 10 of the semiconductor substrate 10 through the gateinsulating film 40.

The diffusion layer 70 is used as a source layer or a drain layer, andmay be used as a part of a LDD (lightly doped drain) structure. In theinstant embodiment, the diffusion layer 70 is used as an extension layerfor making the LDD structure doubling the source or drain layer. Byusing the source or drain layer of the LDD structure, generation of hotelectrons and a short-channel effect can be prevented.

In the instant embodiment, the impurity used for extension ion injection75 may be boron, for example. The dose of boron may be approximately5×10¹⁴ cm⁻², for example, and the injection energy is approximately 10keV, for example. Therefore, the diffusion layer 70 has a p-typeconductivity. The depth of the diffusion layer from the top surface 12is around 40 nm.

Thereafter, a silicon oxide film is deposited to cover the top surface12 and the gate electrode 60, and a silicon nitride film is depositedthereon. Both the silicon oxide film and the silicon nitride film may bedeposited by LP-CVD, for example. The silicon oxide film is used as aliner layer having the role of stopping etching when the silicon nitridefilm is etched.

As shown in FIG. 5, the silicon nitride film and the silicon oxide filmare selectively removed by anisotropic etching, and they partly remainas a sidewall liner layer 80 and a sidewall protective layer 85 on thesidewall of the gate electrode 60. The sidewall liner layer 80 and thesidewall protective layer 85 are approximately 5 nm thick and 20 nmthick, respectively, for example.

The sidewall liner layer 80 and the sidewall protective layer 85 protectthe sidewall of the gate electrode 60, and also function as a spacerduring ion injection for forming source and drain diffusion layer 72.That is, the sidewall protective layer 85 makes the source and drainlayer 72 implanted in a self-aligned manner. Thereby, the diffusionlayers 70, 72 form a LDD structure. In the instant embodiment, depth ofthe diffusion layer 72 is approximately 50 nm.

After the silicon oxide film and the silicon nitride film are removed,the diffusion layer 70 or 72 on the top surface of the semiconductorsubstrate 10 is exposed. The crystal surface of the top surface 12 ofthe semiconductor substrate 10 assists epitaxial growth of a siliconsingle-crystal layer on the top surface 12.

On the other hand, exposure of the crystal surface of the top surface 12of the semiconductor substrate 10 to air causes a silicon oxide 90 to beproduced by oxidation of silicon on the top surface.

As shown in FIG. 6, an amorphous silicon layer 100 is then depositedover the exposed top surface 12 and the gate electrode 60. The amorphoussilicon 100 is formed by LP-CVD, for example, using silane (SiH₄) in anatmosphere held at approximately 600° C. In the instant embodiment, thethickness of the amorphous silicon is about 50 nm.

As shown in FIG. 7, ions are injected into the semiconductor substrate10 through its interface with the amorphous silicon 100. Injectionmaterial for this ion injection 110 may be, for example, germanium,arsenic, boron, argon, which is an inactive substance, or any of theircongener elements. In the instant embodiment, germanium is used as theinjection material for the ion injection 110. The quantity of theinjection material for the ion injection 110 may be, for example,approximately 1×10¹⁵ cm⁻², and the injection energy is about 7 kev, forexample.

Germanium ions accelerated by the ion injection 110 break through to thesilicon oxide 90 through the amorphous silicon layer 100, and pushoxygen contained in the silicon oxide 90 from the interface between thesemiconductor substrate 10 and the amorphous silicon layer 100 to belowthe top surface 12 of the semiconductor substrate 10. That is, injectedgermanium ions knock against interfacial oxygenexisting along theinterface between the semiconductor substrate 10 and the amorphoussilicon layer 100, pushing it below the top surface 12.

The dose of germanium is determined by the quantity of the silicon oxide90 or interfacial oxygen. The quantity of the silicon oxide 90 orinterfacial oxygen depends on various conditions upon exposing the topsurface 12 of the semiconductor substrate 10 to air, such as, theduration of time of exposure of the top surface 12 to air, thetemperature, the oxygen concentration in the ambient air, and so on.Normally, these conditions are maintained constant throughout themanufacturing process of the semiconductor device. Therefore, the doseof germanium may be determined in accordance with the conditions in themanufacturing process of the semiconductor device.

In the instant embodiment, the quantity of interfacial oxygen betweenthe semiconductor substrate 10 and the amorphous silicon layer 100 isdeemed to be about 1×10¹⁵ cm⁻². Thus the dose of germanium is 1×10¹⁵cm⁻², equal to the quantity of the interfacial oxygen. For the purposeof reliably knocking more interfacial oxygen below the top surface 12,the dose of germanium is preferably equal to or more than theinterfacial oxygen existing along the interface between thesemiconductor substrate 10 and the amorphous silicon layer 100.

In contrast, for the purpose of preventing the semiconductor substrate10 from excessive damage, the dose of germanium may be less than thequantity of the interfacial oxygen.

Injection energy of germanium must be large enough for germanium topenetrate the amorphous silicon layer 100. On the other hand, germaniumand oxygen may cause a leakage at the junction between the diffusionlayer 72 and the well region 20 if they are injected or knocked deeperthan the depth of the diffusion layer 72. Therefore, injection energy ofgermanium is preferably limited to a level prohibiting germanium frompenetrating the diffusion layer 72.

In the instant embodiment, germanium or oxygen is preferably injected orknocked shallower than the depth of the diffusion layer 72. However, incase the device does not include the diffusion layer 72 as the sourceand drain layer and only includes the diffusion layer 70 as theextension layer, germanium and oxygen are preferably injected or knockedshallower than the depth of the diffusion layer 70. In this case, sincethe diffusion is shallower than the diffusion layer 72, injection energyof germanium is adjusted to be lower than the injection energy used inthis embodiment.

As shown in FIG. 8, the amorphous silicon layer 100 is annealed. As aresult of this annealing, the amorphous silicon layer 100 on thediffusion layers 70, 72 is epitaxially grown to form a siliconsingle-crystal layer 120. That is, in the instant embodiment, to obtainthe silicon single-crystal layer 120, the SPE technique is used. In theinstant embodiment, the annealing is carried out in a hydrogenatmosphere held at approximately 600° C. in an LP-CVD apparatus.

At the time of annealing, interfacial oxygen is already knocked belowthe top surface of the semiconductor substrate 10, and the silicon oxide90 no longer exists between the semiconductor substrate 10 and theamorphous silicon layer 100. Therefore, the entirety of the amorphoussilicon layer 100 is in contact with silicon crystals on the top surface12 of the source and drain diffusion layers 70, 72. As a result, theamorphous silicon layer 100 can epitaxially grow with sufficientthickness and uniform quality on the diffusion layers 70, 72 and canchange to the silicon single-crystal layer 120.

On the other hand, top surfaces of the device-isolating portion 30, gateelectrode 60 and sidewall protective layer 85 are made of a siliconoxide, polycrystalline silicon and silicon nitride, respectively.Therefore, the amorphous silicon layer 100 does not epitaxially grow onthe device-isolating portion 30, gate electrode and sidewall protectivelayer 85, and remains as the amorphous silicon layer or changes to apolycrystalline silicon layer.

As shown in FIG. 9, the layer 100′ of amorphous silicon andpolycrystalline silicon is selectively etched relative to the siliconsingle-crystal layer 120. In this embodiment, this etching is carriedout by LP-CVD using chlorine gas diluted to approximately 10% byhydrogen within the same chamber as that used for deposition of theamorphous silicon layer 100. Etching selectivity of amorphous siliconrelative to single-crystal silicon is 10 or more.

In the instant embodiment, a common chamber is used both for epitaxialgrowth of the silicon single-crystal layer 120 and for selective etchingof the amorphous silicon layer and the polycrystalline silicon layer100′. This contributes to shortening the manufacturing process of thesemiconductor device, enhancing the productivity and reducing themanufacturing cost. Additionally, the quality of the siliconsingle-crystal layer 120 is improved.

Even when different chambers are used for those steps, substantially thesame effect is obtained by using a so-called cluster tool and carryingout a series of epitaxial growth, selective etching, and so on.

When the amorphous silicon layer and the polycrystalline silicon layer100′ are selectively etched, the sidewall of the gate electrode 60 isprotected by the sidewall liner layer 80 and the sidewall protectivelayer 85. Therefore, the sidewall of the gate electrode 60 is notetched. The top surface of the gate electrode 60 is in direct contactwith the polycrystalline silicon layer 100′. Since the gate electrode 60is made of polycrystalline silicon which is same as the polycrystallinelayer 100′, it is immaterial that the polycrystalline layer 100′ is notremoved completely but partly remains. On the other hand, since the gateelectrode 60 is sufficiently thick relative to the amorphous siliconlayer and the polycrystalline silicon layer 100′, it is acceptable thatthe top surface of the gate electrode 60 is over-etched slightly.

As shown in FIG. 10, a metal is next deposited on the siliconsingle-crystal layer 120. This metal may be, for example, cobalt,nickel, titanium, or the like. The deposited metal acts on silicon ofthe silicon single-crystal layer 120 and forms a silicide layer 130 usedfor reducing the contact resistance.

Since the metal interacts with silicon of the silicon single-crystallayer 120, it does not erode silicon in the diffusion layers 70, 72underlying the top surface 12 of the semiconductor substrate 10. Even ifthe metal erodes the diffusion layers 70, 72, the quantity of the erodedsilicon in the diffusion layers 70, 72 is quite small. Therefore, thesilicide layer 130 does not protrude through the bottom of the diffusionlayers 70, 72. Thus leakage does not occur between the source and draindiffusion layers 70, 72 and the substrate 10 or well region 20. That is,this embodiment can attain sufficient effects of the ElevatedSource-Drain technique.

Through some subsequent steps (not shown), including the step of forminga contact and a step of forming a interconnections, the semiconductordevice according to the instant embodiment is completed.

As explained above, the semiconductor device manufacturing methodaccording to this embodiment does not anneal the semiconductor substrate10 at 600° C. or higher temperatures after forming the diffusion layers70, 72. Therefore, the embodiment can form the diffusion layers 70, 72relatively shallow from the top surface 12 of the semiconductorsubstrate 10, and can prevent punch-through or other short channeleffect even when the semiconductor substrate is downsized extremely.

Next explained is the configuration of the semiconductor substrate 200made by the manufacturing method according to the first embodiment.

FIG. 11A is an enlarged cross-sectional view of the semiconductor device200 manufactured by the semiconductor device manufacturing methodaccording to the first embodiment. The semiconductor device 200according to this embodiment includes the semiconductor substrate 10;gate insulating film 40 formed on the top surface 12 of thesemiconductor substrate 10; and gate electrode 60 formed on the gateinsulating film 40. In a part of the semiconductor substrate 10 on oneside of the gate electrode 60, the source-side extension layer 70 aconnected to the source electrode (not shown) is formed in aself-aligned manner making use of the sidewall of the gate electrode 60.Similarly, in another part of the semiconductor substrate 10 on theother side of the gate electrode 60, the drain-side extension layer 70 bconnected to the drain electrode (not shown) is formed in a self-alignedmanner making use of the sidewall of the gate electrode 60.

On the gate electrode 60, the sidewall protective layer 85 lies via theliner layer 80 to protect the gate electrode 60. In a region of thesemiconductor substrate on one side of the gate electrode 60, the sourcelayer 72 a is formed in a self-aligned manner using the sidewallprotective layer 85 as a spacer. Similarly, in another region of thesemiconductor substrate 10 on the other part of the gate electrode 60,the drain layer 72 b is formed in a self-aligned manner using thesidewall protective layer 85 as a spacer.

The instant embodiment includes both the source-side extension layer 70a plus the drain-side extension layer 70 b (hereinbelow collectivelycalled diffusion layer 70 as well) and the source layer 72 a plus thedrain layer 72 b (hereinbelow collectively called diffusion layer 72 aswell). However, even when the semiconductor device has only one ofdiffusion layer 70 or 72, the effects of the embodiment of the inventionwill be maintained.

The semiconductor device 200 further includes a silicide layer 130overlying the diffusion layer 70 or 72. The silicide layer 130 ispreferably connected directly to the diffusion layers 70, 72 to reducethe contact resistance between the diffusion layers 70, 72 and thesource or drain electrode.

However, for the purpose of completely preventing silicon in thediffusion layers 70, 72 from erosion in the process of forming thesilicide layer 130, a silicon single-crystal layer 120 may residebetween the silicide layer 130 and the diffusion layers 70, 72. In thiscase, the silicon single-crystal layer interposed between the silicidelayer 130 and the diffusion layers 70, 72 are doped with an impurity.

FIG. 11B is a graph showing changes of oxygen and germaniumconcentrations with depth from the top surface 12 of the semiconductordevice 200. Let the depth of the top surface 12 be 0 (zero). Then thedepth of the oxygen concentration peak, where the oxygen concentrationis maximized, and the depth of the germanium concentration peak, wherethe germanium concentration is maximized, is denoted by d₁, and thedepth of the diffusion layer 72 is denoted by d₂.

According to the graph of FIG. 11B, the oxygen concentration peak andthe germanium concentration peak are in a level lower than the topsurface 12. Germanium and interfacial oxygen are injected or knocked tosubstantially the same depth d₁ from the top surface 12. Therefore, thedepth of the oxygen concentration peak from the top surface 12 of thesemiconductor device 10 is approximately equal to the depth of thegermanium concentration peak from the top surface 12 of thesemiconductor substrate 10.

Energy for injection of germanium is adjusted to prohibit germanium andoxygen from penetrating the diffusion layer 72 and reaching the n well20. Therefore, according to the instant embodiment, both the depth d₁ ofthe oxygen concentration peak and the depth d₁ of the germaniumconcentration peak are shallower than the depth d₂ of the diffusionlayer 72.

As explained above, the dose of germanium is determined by the quantityof interfacial oxygen. If a larger quantity of germanium thaninterfacial oxygen is injected, then the concentration of germaniumcontained in each unit surface area of the semiconductor substrate 10 isequal to or larger than the concentration of oxygen contained in eachunit surface area of the semiconductor substrate 10. That is, the valueof the germanium concentration peak is equal to or larger than the valueof the oxygen concentration peak.

In the instant embodiment, the dose of germanium is substantially equalto the quantity of interfacial oxygen. Therefore, In FIG. 11B, the peakvalue of germanium concentration is approximately equal to the peakvalue of oxygen concentration. As a result, germanium can knocksubstantially all interfacial oxygen without damaging the top surface 12excessively.

The oxygen concentration being substantially zero on the top surface 12demonstrates that the silicon oxide does not exist on the top surface12. Therefore, the silicon single-crystal layer grows with a sufficientthickness and uniform quality on the diffusion layers 70, 72. Thesufficiently thick and uniform-quality silicon single-crystal layercontributes to forming a sufficiently thick and uniform silicide-layer130 without eroding silicon in the diffusion layers 70, 72 excessively.

In case the semiconductor device 200 is downsized, it needs diffusionlayers 70, 72 higher in impurity concentration and shallower instructure. In such a case, the instant embodiment can fabricate asilicide layer 130 that maintains a low contact resistance withouteroding the shallow diffusion layers 70, 72.

Thus the semiconductor device according to the embodiment can overcomethe short-channel effect, an increase of the contact resistance andother problems caused by microminiaturization.

FIGS. 12 through 19 are enlarged cross-sectional views of asemiconductor substrate under different, sequential processes of asemiconductor device manufacturing method according to the secondembodiment of the invention. The same components as those of thesemiconductor substrate according to the first embodiment are labeledwith the same reference numerals.

The second embodiment has a difference from the first embodiment informing a top surface protective layer 88 on the top surface of the gateelectrode 60 (FIGS. 13 through 19).

As shown in FIG. 12, the n-well region 20, device-isolating portion 30and gate insulating film 40 are formed in the same manner as the firstembodiment, and a polycrystalline silicon layer 65 is formed on the gateinsulating film 40.

As shown in FIG. 13, a silicon nitride film 88 is next formed bydepositing a silicon nitride and next patterning it by usingphotolithography. In the instant embodiment, the thickness of thesilicon nitride film 88 is approximately 50 nm.

As shown in FIG. 14, next using the silicon nitride film 88 as a mask,the polycrystalline silicon layer 65 is etched to form the gateelectrode.

As shown in FIG. 15, the liner layer 80, sidewall protective layer 85and diffusion layers 70, 72 are formed in the same manner as the firstembodiment. Additionally, the amorphous silicon layer 100 is formed onthe top surface 12 of the silicon substrate 10 and the gate electrode60. Here again, the silicon oxide 90 is produced between the top surface12 and the amorphous silicon layer 100.

As shown in FIG. 16, germanium ions are next injected into thesemiconductor substrate through its interface with the amorphous silicon100. Thereby, interfacial oxygen is knocked downward of the top surface12 of the semiconductor substrate 10.

As shown in FIG. 17, the semiconductor substrate 10 is annealed at atemperature around 600° C. Since the interfacial oxygen is alreadyknocked below the top surface of the semiconductor substrate 10, theamorphous silicon layer 100 can change to the silicon single-crystallayer with sufficient thickness and uniform quality on the diffusionlayers 70, 72.

On the other hand, the amorphous silicon layer 100 does not epitaxiallygrow on the device-isolating portion 30, sidewall protective layer 85and top surface protective layer 88, and it remains in the amorphousphase, or changes to a polycrystalline silicon layer.

As shown in FIG. 18, the amorphous silicon layer or polycrystallinesilicon layer 100′ is next etched selectively relative to the siliconsingle-crystal layer 120.

In this embodiment, the top surface protective layer 88 prevents thegate electrode 60 from being etched. That is, the top surface protectivelayer 88 functions as an etching-stopper. As a result, while the gateelectrode 60 is not etched, the amorphous silicon layer 100′ issufficiently etched. Therefore, the instant embodiment reliably preventsover-etching of the gate electrode 60 even when the gate electrode 60 isrelatively thin.

In the instant embodiment, the etching of the amorphous silicon layer100 or polycrystalline silicon layer 100′ may be carried out at 700° C.or a higher temperature. This contributes to increasing the etchingspeed, and reducing the time for the etching step of the amorphoussilicon layer or polycrystalline silicon layer 100′ than that in thefirst embodiment. Thus the second embodiment enhances the productivityof the semiconductor device and reduces its manufacturing cost.

As shown in FIG. 19, a metal is deposited on the silicon single-crystallayer 120 to form the silicide layer 130 in the same manner as the firstembodiment.

Through further steps, including the step of forming the contact and thestep of forming the interconnections (not shown), the semiconductordevice according to the instant embodiment is completed.

The second embodiment also has the same effects as those of the firstembodiment. The second embodiment, which protects both the sidewall andthe top surface of the gate electrode, need not take account ofover-etching of the gate electrode 60. Additionally, the secondembodiment has another effect, namely, shortening the time required foretching the amorphous silicon layer or polycrystalline silicon layer100′ than that of the first embodiment.

Even when replacing n-type semiconductors with p-type semiconductors andreplacing p-type semiconductors with n-type semiconductors, effects ofthe second embodiment remain.

The semiconductor manufacturing method according to any of the foregoingembodiments can form the silicon single-crystal layer available for usewith the Elevated Source-Drain technique on the source and draindiffusion layers at a relatively low temperature.

The semiconductor device according to any of the foregoing embodimentshas the silicide layer made by the Elevated Source-Drain technique to beuniform in thickness and quality, and it is available for more enhancedmicrominiaturization than existing semiconductor devices whilemaintaining low contact resistance between the source and draindiffusion layers and the source and drain electrodes.

1.-10. (Canceled).
 11. A method of manufacturing a semiconductorsubstrate comprising: forming a gate insulating film on the top surfaceof a semiconductor substrate; forming a gate electrode on the gateinsulating film; forming diffusion layers in a self-aligned manner inthe semiconductor substrate on opposite sides of the gate electrode;forming an amorphous layer on the top surface of the semiconductorsubstrate above the diffusion layers; implanting ions of an injectionsubstance into the semiconductor substrate through an interface thereofwith the amorphous layer; annealing the semiconductor substrate at arelatively low temperature to partly change the amorphous layer to asingle-crystal layer; and sputtering a metal onto the single-crystallayer and thereby forming a silicide layer from the single crystal andthe metal.
 12. The method according to claim 11, wherein, during theannealing of the semiconductor substrate, only selective parts of theamorphous layer located on the diffusion layers are changed to asingle-crystal layer, and the other parts of the amorphous layer are notchanged or are changed to a polycrystalline layer, and the methodfurther comprising: selectively etching the amorphous layer or thepolycrystalline layer after said annealing.
 13. The method according toclaim 11, wherein the injection substance is germanium, its congenerelement, arsenic, its congener element, boron, its congener element,argon or its congener element.
 14. The method according to claim 12,wherein the injection substance is germanium, its congener element,arsenic, its congener element, boron, its congener element, argon or itscongener element.
 15. The method according to claim 11, whereinannealing the semiconductor substrate at a temperature not higher than600° C., during the annealing of the semiconductor substrate.
 16. Themethod according to claim 12, wherein annealing the semiconductorsubstrate at a temperature not higher than 600° C., during the annealingof the semiconductor substrate.
 17. The method according to claim 13,wherein annealing the semiconductor substrate at a temperature nothigher than 600° C., during the annealing of the semiconductorsubstrate.
 18. The method according to claim 14, wherein annealing thesemiconductor substrate at a temperature not higher than 600° C. duringthe annealing of the semiconductor substrate.
 19. The method accordingto claim 12, further comprising: forming a protective layer to cover thesidewall of the gate electrode and the top surface of the gate electrodebefore forming the amorphous layer, wherein the amorphous layer and thepolycrystalline layer are etched at a temperature not lower than 700° C.during the etching the amorphous layer or the polycrystalline layer.